1. Field of the Invention
The present invention relates to an integrated circuit device having lower wiring and upper wiring connected to each other by an interconnect line, and more particularly to an integrated circuit device fabricated according to the dual damascene process.
2. Description of the Related Art
To meet present demands for integrated circuits of higher performance and smaller patterns, there have been studied various processes for fabricating such integrated circuits and materials to be used in such integrated circuits. For example, while polysilicon or aluminum has heretofore been widely used as the wiring material in integrated circuits, a material having a lower resistance is required to achieve higher performance and smaller patterns for integrated circuits.
It has been proposed to make fine wiring in integrated circuits of copper. However, the properties of copper make it difficult to pattern itself by way of etching, and the corrosion resistance of copper is poor. In view of these difficulties of copper, it is preferable to employ the dual damascene process to fabricate an integrated circuit which has horizontal lower and upper wiring made of a metal such as copper and connected to each other with a vertical interconnect line.
In the integrated circuit thus fabricated by the dual damascene process, i.e., a dual damascene circuit, since the horizontal lower and upper wiring are connected to each other by the vertical interconnect line, it is necessary to form an upper interlayer film on the upper surface of a lower interlayer film in which lower wiring is embedded, form an upper groove and a via hole in the upper interlayer film, and embed upper wiring and the interconnect line in the upper groove and the via hole.
There is a fabrication process in which an upper interlayer film is made as a single layer of an organic polymer or MSK (Methyl Silsesquioxane), a via hole is formed in the upper interlayer film by first photo etching from its upper surface to a certain depth, and an upper groove is formed in the upper interlayer film and the via hole is simultaneously extended to the lower surface by second photo etching.
There is another fabrication process in which an upper interlayer film is comprised of a first layer, a barrier insulating film, and a second layer, a via hole is formed in the second layer and the barrier insulating film by first photo etching, and an upper groove is formed in the second layer and a via hole is simultaneously formed in the first layer from the opening in the barrier insulating film by second photo etching.
According to the first fabrication process described above, since the upper interlayer film is formed as a single layer, a resultant dual damascene circuit is simple in structure, the number of steps of the fabrication process is relatively small, and the effective permittivity of the dual damascene circuit can be reduced because the upper interlayer film may be formed of a low-density material. However, as the upper groove and the via hole are simultaneously formed in the single-layer upper interlayer film, it is difficult to form the upper groove and the via hole to a good shape, and it is particularly difficult to form the upper groove to a desired depth due to mircroloading.
According to the first fabrication process described above, since the upper interlayer film is formed as a single layer, a resultant dual damascene circuit is simple in structure, the number of steps of the fabrication process is relatively small, and the effective permittivity of the dual damascene circuit can be reduced because the upper interlayer film may be formed of a low-density material. However, as the upper groove and the via hole are simultaneously formed in the single-layer upper interlayer film, it is difficult to form the upper groove and the via hole to a good shape, and it is particularly difficult to form the upper groove to a desired depth due to microloading.
Furthermore, since the high-density material which the barrier insulating film is made of is generally of high permittivity, the effective permittivity of the dual damascene circuit is increased. According to the second fabrication process, the via hole tends to have a bowing profile due to excessive etching because the upper groove and the via hole are simultaneously formed.
An integrated circuit and a process of manufacturing same, which solve the above problems, are disclosed in Japanese laid-open patent publication No. 10112503.
As shown in FIG. 1 of the accompanying drawings, dual damascene circuit 100 as the disclosed integrated circuit has lower interlayer film 101 on which there are successively deposited insulating layer 102, low-permittivity layer 103, and mask layer 104. Insulating layer 102 and mask layer 104 are made of silicon oxide such as SiO2, SiOx, SiOF, or the like, and low-permittivity layer 103 is made of an organic material such as polytetrafluoroethylene, polyanile ether fluoride, polyimide fluoride, etc.
Lower groove 111 is formed in lower interlayer film 101 from its upper surface to a certain depth, and lower wiring 105 is embedded in lower groove 111. Via hole 112 is formed in insulating layer 102 all the way from the upper surface to the lower surface thereof. Interconnect line 106 is embedded in via hole 112.
Upper groove 113 is formed in low-permittivity layer 103 all the way from the upper surface to the lower surface thereof, and upper wiring 107 is embedded in upper groove 113. Lower wiring 105, interconnect line 106, and upper wiring 107 are made of aluminum alloy, and lower wiring 105 and upper wiring 107 are connected to each other by interconnect line 106.
A process of fabricating dual damascene circuit 100 having the above structure will briefly be described below.
First, lower wiring 105 is embedded in lower groove 111 which is formed in lower interlayer film 101 from its upper surface to a certain depth. Insulating layer 102, low-permittivity layer 103, and mask layer 104, which are made of silicon oxide, are successively grown on the upper surface of lower interlayer film 101 with lower wiring 105 embedded therein.
Then, a resist mask (not shown) having an opening shaped like upper groove 113 is formed on the upper surface of mask layer 104. An opening corresponding to upper groove 113 is formed in mask layer 104 through the resist mask by plasma etching, after which the resist mask is removed.
A resist mask (not shown) having an opening shaped like via hole 112 is formed on the upper surface of mask layer 104 and the upper surface of an exposed portion of low-permittivity layer 103. Via hole 112 is formed in low-permittivity layer 103 and insulating layer 102 through the resist mask by plasma etching, after which the resist mask is removed.
Upper groove 113 is formed in low-permittivity layer 103 through mask layer 104 by plasma etching. Upper groove 113 and via hole 112 are filled with aluminum alloy, and the upper surface of the assembly is polished by CMP (Chemical Mechanical Polishing), thus completing dual damascene circuit 100 which includes lower wiring 105, interconnect line 106, and upper wiring 107 made of Cu and connected together.
With dual damascene circuit 100, since low-permittivity layer 103 and insulating layer 102 have high etching selectivity with respect to each other, it is possible to form upper groove 113 and via hole 112 to a desired shape to allow interconnect line 106 and upper wiring 107 to have good electric characteristics. However, it is difficult to lower the effective permittivity of entire dual damascene circuit 100 because the insulating layer 102 is made of silicon oxide having a high permittivity ranging from 4.2 to 4.3.
Though not disclosed in Japanese laid-open patent publication No. 10-112503, since interconnect line 106 serves to connect upper wiring 107 to lower wiring 105, lower wiring 105 is laid in a position where interconnect line 106 is formed. If, however, plasma etching for forming via hole 112 reaches lower wiring 105, then lower wiring 105 is corroded and has its electric characteristics lowered.
To eliminate the above drawback, it has been known to protect lower wiring 105 from plasma etching for forming via hole 112 with a barrier insulating film (not shown) layered over the upper surface of lower wiring 105. Such a barrier insulating film is generally formed of silicon nitride.
In dual damascene circuit 100, inasmuch as insulating layer 102 is made of silicon oxide, it has low etching selectivity with respect to the barrier insulating film of silicon nitride. Therefore, when insulating layer 102 is subjected to plasma etching, it is highly likely for the barrier insulating film to be etched away, failing to protect lower wiring 105 effectively.